Relentless efforts at miniaturization are bringing traditional CMOS devices to the limit where the device characteristics are governed by quantum phenomena; in such regimes, perfect control is impossible to achieve. This has engendered a need for finding alternative new materials to fabricate devices that will possess at least the same or even better performance than existing CMOS devices but with greater control.
The miniaturization of CMOS devices has hitherto been governed by a trend—often called Moore's law—in which electronic components shrink in size by half every 30 months. The International Technology Roadmap for Semiconductors (ITRS) has established a projected growth curve according to this model. The demands for speed, high integration level, high performance and low production costs attendant on such a rate of progress are very stringent. Consequently, the problems associated with the physical and electrical characteristics of traditional materials used for making devices have escalated. Hence there is a need to search for alternative solutions to the problems that will ultimately impede the progress of silicon technology in the immediate future. This means that devising innovative material and process solutions is critical to sustaining the projected rate of growth.
The choice of new materials is however limited by factors such as compatibility with existing production methods, reproducibility of manufacture and cost. Some problems that existing technology materials have faced are as follows.
High power consumption due to leakage current: currently, the device performance is degraded due to high leakage current through gate oxide (which is very thin). This in turn increases the leakage current in the off state, and hence increases power consumption, which in turn reduces the life time of a battery.
Poor performance of Cu interconnects: due to its low resistivity, copper is used for making interconnects that are used for connecting various components to one another, as well as devices and circuits with the outside world. Due to the dramatic reduction in the size of the components, interconnects based on copper material are now showing poor performance in terms of current carrying capacity and lifetime of the wires. This in turn reduces the lifetime of a processor. No solution currently exists for interconnects that will efficiently connect the devices in a circuit with those outside of the circuit, in time to meet the projected demand for current density over the next several years.
Demand for high aspect ratio structures: today the aspect ratio of contact holes for interconnects in DRAM staked capacitors has reached 12:1 and is expected to increase to 23:1 by the year 2016. Creating such high aspect ratio contacts with straight walls poses substantial technological challenges, not least because void-free filling with metals (also known as vias) of such high aspect ratio features is extremely difficult.
High heat dissipation: modern microprocessors generate inordinate amounts of heat. Heat dissipation has been increasing steadily as the transistor count and clock frequency of computer processors has increased. In particular, for example, copper interconnects of the sizes required for current and future devices generate so much heat that their electrical resistance is increased, thereby leading to a decreased capacity to carry current. However a practical solution for cooling of such systems which will not eventually exceed the power budget for processors has yet to be found.
In short, for all these reasons, it has become necessary to search for alternative materials and processing technology.
Carbon nanostructures, including carbon nanotubes (CNTs) and nanofibers, are considered to be some of the most promising candidates for future developments in nano-electronics, nano-electromechanical systems (NEMS), sensors, contact electrodes, nanophotonics, and nano-biotechnology. This is due principally to their one dimensional nature, and their unique electrical, optical and mechanical properties. In contrast to the fullerenes, such as C60 and C70, whose principal chemistry is based on attaching specific functionalities thereby giving rise to specific properties, CNTs offer an almost limitless amount of variation through design and manufacture of tubes of different diameters, pitches, and lengths. Furthermore, whereas the fullerenes offer the possibility of making a variety of discrete molecules with numerous specific properties, carbon nanotubes provide the possibility to make molecular-scale components that have excellent electrical and thermal conductivity, and strength. (See, e.g., Nanoelectronics and Information Technology, R. Waser (Ed.), Wiley-VCH, 2003, at chapter 19.)
Carbon nanotubes and carbon nanofibers have been considered for both active devices and as interconnect technology at least because their electrical and thermal properties and their strength. For example, the high electron mobility of carbon nanotubes (79,000 cm2/Vs) surpasses that of state-of-the-art MOSFET devices (see, e.g., Durkop, T., et al., Nano Letters, 4(1), 35, (2004)). Furthermore, the extremely high current carrying capacity of carbon nanotubes (1010 A/cm2) (see, e.g., Wei, B. Q., et al., Appl. Phys. Lett., 79(8), 1172, (2001)), when compared with copper interconnects (˜106 A/cm2), means that carbon nanotubes potentially possess the solution to the severe problems for interconnects projected in ITRS.
The anisotropic thermal conductivity of nanotubes/nanofibers (6,000 W/Km) (see, e.g., Hoenlien, W., et al., IEEE Trans. Compon. and Packaging Tech., 27(4), 629, (2004)) is also exceptionally promising for solving problems of heat dissipation.
Finally, the high E-modulus (representing the strength of a material) of individual nanotubes (as high as 1 TPa) has made them a good choice for both composite materials and for nanoelectromechanical devices.
In general, it is highly desirable to fabricate electronic devices that are compatible with existing complementary metal oxide semiconductor (CMOS) fabrication techniques. A prerequisite for exploring CNTs in an industrial process is to be able to control mass production of devices with high reproducibility. Due to high purity and high yield, chemical vapor deposition (CVD) is a popular and advantageous growth method that offers the potential to grow nanotubes at an exact location with control over their length, diameter, shape and orientation.
Hence for many electronic, nanoelectromechanical systems and interconnect applications the integration possibilities of carbon nanostructures into existing CMOS-based electronic industrial manufacturing processes is expected to be a ground breaking technological breakthrough. However, there are many engineering and materials issues inherent to CMOS-compatible device fabrication processes that need to be addressed before such integration can take place. Solutions to these issues have so far been long-awaited.
For instance, there are problems related to growth of nanostructures. Although numerous techniques have been developed and demonstrated to produce carbon based nanostructures, all possess drawbacks regarding mass production and integration into existing industry manufacturing processes. Prominent drawbacks are: (a) control over predictable morphology with either semiconducting or metallic properties, (b) precise localization of the grown individual structures, and (c) predictable electrical properties at the interface between the grown nanostructures and the substrate. There is no known single solution to solve all the aforementioned drawbacks. The most prominent techniques for synthesizing carbon nanostructures include arc discharge (see, e.g., Iijima, S., Nature, 354, 56, (1991); and Kratschmer, W.; Lamb, L. D.; Fostiropoulos, K.; Huffinan, D. R., Nature, 347, 354, (1990)), laser vaporization (see, e.g., Kroto, H. W.; Heath, J. R.; O'Brien, S. C.; Curl, R. F.; Smalley, R. E. Nature, 318, 162, (1985)), catalytic chemical-vapor deposition (CCVD), also referred to as CVD, (Cassell, A. M.; Raymakers, J. A.; Jing, K.; Hongjie, D., J. Phys. Chem. B, 103, (31), (1999)), and catalytic plasma enhanced chemical-vapor deposition (C-PECVD) (Cassell, A. M.; Qi, Y.; Cruden, B. A.; Jun, L.; Sarrazin, P. C.; Hou Tee, N.; Jie, H.; Meyyappan, M., Nanotechnology, 15(1), 9, (2004); and Meyyappan, M.; Delzeit, L.; Cassell, A.; Hash, D., Plasma Sources, Science and Technology, 12(2), 205, (2003)), all of which references are incorporated herein by reference in their entirety. Due to high purity and high yield, chemical vapor deposition (CVD) is a popular and advantageous growth method, and indeed, among all of the known growth techniques, CMOS compatibility has been demonstrated only for the CCVD method. (See, Tseng, et al. (Tseng, Y.-C.; Xuan, P.; Javey, A.; Malloy, R.; Wang, Q.; Bokor, J.; Dai, H. Nano Lett. 4(1), 123-127, (2004), incorporated herein by reference) where a monolithic integration of nanotube devices was performed on n-channel semiconductor (NMOS) circuitry.)
There are specific problems related to control of the properties of grown materials. Even though numerous different alternative growth methods exist for growing carbon nanostructures, controlling the interface properties between the nanostructures and the substrates, the body of the nanostructures, and the tip of the nanostructures are not yet demonstrated to be well controlled by utilizing a single method of growth.
CVD typically employs a metal catalyst to facilitate carbon nanostructure growth. The main roles of the catalyst are to break bonds in the carbon carrying species and to absorb carbon at its surface and to reform graphitic planes through diffusion of carbon through or around an interface (see, e.g., Kim, M. S.; Rodriguez, N. M.; Baker, R. T. K., Journal of Catalysis, 131, (1), 60, (1991); and Melechko, A. V.; Merkulov, V. I.; McKnight, T. E.; Guillom, M. A.; Klein, K. L.; Lowndes, D. H.; Simpson, M. L., J. App. Phys., 97(4), 41301, (2005), incorporated herein by reference).
However, the growth of nanotubes is usually carried out on silicon or other semiconducting substrates. Growth from such metal catalysts on conducting metal substrates or metal underlayers is almost lacking. This is because it has been found that it is hard to make a good contact between a growing nanostructure and a conducting substrate with good quality grown nanostructures in terms of control over diameter, length and morphology. Nevertheless, for making CMOS-compatible structures, it is necessary to use a conducting substrate. In particular, this is because a metal substrate, or base layer, acts as bottom electrode for electrical connection to the nanostructures.
Nevertheless, growth of nanostructures on CMOS compatible conducting substrates has proved to be far from trivial, at least because different metals require different conditions, and also because it has proven difficult to control the properties of the nanostructures grown on such substrates with predictable control over diameter, length and morphology of the grown structures and with predictable interface properties between the nanostructures and the substrate.
A method for producing arrays of carbon nanotubes on a metal underlayer, with a silicon buffer layer between the metal underlayer and a catalyst layer, is described in U.S. Patent Application Publication No. 2004/0101468 by Liu et al. According to Liu, the buffer layer prevents catalyst from diffusing into the substrate and also prevents the metal underlayer from reacting with carbon source gas to, undesirably, form amorphous carbon instead of carbon nanostructures. In Liu, the process involves, inconveniently, annealing the substrate in air for 10 hours at 300-400° C. to form catalyst particles, via oxidation of the catalyst layer, prior to forming the nanostructures. Each catalyst particle acts as a seed to promote growth of a nanostructure. The method of Liu, however, does not permit control of the composition or properties of the nanostructures and the nanotubes produced are curved and disorganized.
An additional goal is fabrication of carbon based nano-electro mechanical structures (NEMS). Extensive theoretical analysis on two-terminal and three-terminal carbon based NEMS (C-NEMS) structures were performed by Dequesnes et al. (Dequesnes, M.; Rotkin, S. V.; Aluru, N. R., Nanotechnology, 13(1), 120, (2002)) and Kinaret et al. (Kinaret, J. M.; Nord, T.; Viefers, S., Applied Physics Letters, 82(8), 1287, (2003)) respectively, all of which references are incorporated herein by reference in their entirety. The model developed by Kinaret et al. for three-terminal NEMS device consists of a conducting carbon nanotube (CNT) placed on a terraced Si substrate and connected to a fixed source electrode which they have called it “nanorelay.” Recently Lee et al. (Lee, S. W. L., et al., Nano Letters, 4(10), 2027, (2004), incorporated herein by reference) have demonstrated the characteristics of such three terminal nanorelay structures experimentally. However, the experimental approach by Lee et al. for fabricating such devices is time consuming and the technology is heavily dependent on the sonicated CNF solutions which usually do not possess any control over the length and the diameter of the CNF: the functional part of the device. Therefore, it is desirable to develop a technology for fabricating such structures with predictable behavior.
Accordingly, there is a need for a method of growing carbon nanostructures on a metal substrate in such a way that various properties of the nanostructures can be controlled.
The discussion of the background to the invention herein is included to explain the context of the invention. This is not to be taken as an admission that any of the material referred to was published, known, or part of the common general knowledge as at the priority date of any of the claims.
Throughout the description and claims of the specification the word “comprise” and variations thereof, such as “comprising” and “comprises”, is not intended to exclude other additives, components, integers or steps.